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GALVANTECH, INC.
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
SYNCHRONOUS BURST SRAM PIPELINED OUTPUT
FEATURES
* * * * * * * * * * * * * * * * * Fast access times: 3.5, 3.8, and 4.0ns Fast clock speed: 166, 150, 133, and 117MHz Provide high performance 3-1-1-1 access rate Fast OE# access times: 3.5ns and 3.8ns Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) 3.3V -5% and +10% core power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/O's Clamp diodes to VSSQ at all inputs and outputs Common data inputs and data outputs BYTE WRITE ENABLE and GLOBAL WRITE control Three chip enables for depth expansion and address pipeline Address, data and control registers Internally self-timed WRITE CYCLE Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications Low profile 119 lead, 14mm x 22mm BGA (Ball Grid Array) and 100 pin TQFP packages
256K x 18 SRAM
+3.3V SUPPLY, FULLY REGISTERED INPUTS AND OUTPUTS, BURST COUNTER
GENERAL DESCRIPTION
The Galvantech Synchronous Burst SRAM family employs high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors. The GVT71256D18 SRAM integrates 262,144x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE#), depth-expansion chip enables (CE2# and CE2), burst control inputs (ADSC#, ADSP#, and ADV#), write enables (WEL#, WEH#, and BWE#), and global write (GW#). Asynchronous inputs include the output enable (OE#) and burst mode control (MODE). The data outputs (Q), enabled by OE#, are also asynchronous. Addresses and chip enables are registered with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#). Address, data inputs, and write controls are registered onchip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL# controls DQ1-DQ8 and DQP1. WEH# controls DQ9-DQ16 and DQP2. WEL#, and WEH# can be active only with BWE# being LOW. GW# being LOW causes all bytes to be written. WRITE pass-through capability allows written data available at the output for the immediately next READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The GVT71256D18 operates from a +3.3V power supply. All inputs and outputs are LVTTL compatible. The device is ideally suited for 486, PentiumTM, 680x0, and PowerPCTM systems and for systems that are benefited from a wide synchronous data bus.
OPTIONS
* Timing 3.5ns access/6.0ns cycle 3.8ns access/6.7ns cycle 4.0ns access/7.5ns cycle 4.0ns access/8.5ns cycle Packages 119-lead BGA 100-pin TQFP
MARKING
-3 -4 -5 -6 B T
*
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Web Site www.galvantech.com
Rev. 11/98
Pentium is a trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation. Galvantech, Inc. reserves the right to change products or specifications without notice.
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
WEH# BWE#
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
UPPER BYTE WRITE
D
Q
WEL# GW# CE# CE2 CE2# ZZ OE# ADSP# Power Down Logic
LOWER BYTE WRITE
D
Q
lo byte write hi byte write Output Buffers
ENABLE
D
Q
D
Q
Input Register
A17-A2 ADSC#
Address Register 256K x 9 x 2 SRAM Array
OUTPUT REGISTER
CLR ADV# A1-A0 MODE Binary Counter & Logic
D
Q
DQ1DQ16, DQP1, DQP2
NOTE:
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
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Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 11/98
GALVANTECH, INC.
1 A B C D E F G H J K L M N P R T U 2 3 4 5 A8 A9 6
A16
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
PIN ASSIGNMENT (Top View)
7
A6 A7 CE# CE2 NC NC WEH# WEL# CE2# VCC VSS CLK GW# BWE# OE# ADSC# ADSP# ADV# A8 A9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67
VCCQ
A6 A4 A3
ADSP#
VCCQ
NC CE2 NC
ADSC#
CE2# NC
A7 A2
VCC A12 A15
DQP1
NC NC
DQ9 NC VSS NC VSS
NC DQ10 VSS CE# VSS NC DQ8
VCCQ
NC VSS OE# VSS DQ7
WEH# ADV#
VCCQ
NC DQ11
DQ12
VCCQ
VSS NC DQ6
NC VSS GW# VSS DQ5 NC
VCC
NC VCC NC VCC
VCCQ
NC DQ13 VSS CLK VSS NC DQ4
DQ14
VCCQ
NC VSS NC
WEL#
DQ3 NC NC
VCCQ
DQ15 VSS BWE# VSS
DQ16
NC VSS
DQP2
A1 A0
VCC
VSS DQ2 NC VSS NC DQ1 NC A13 NC ZZ
VCCQ
NC NC
VSS
MODE
A5
NC A10 A11 NC A14 A17
VCCQ
NC NC NC VCCQ VSSQ NC NC DQ9 DQ10 VSSQ VCCQ DQ11 DQ12 NC VCC NC VSS DQ13 DQ14 VCCQ VSSQ DQ15 DQ16 DQP2 NC VSSQ VCCQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin PQFP or 100-pin TQFP
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A10 NC NC VCCQ VSSQ NC DQP1 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ NC NC NC
NC
NC
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TOP VIEW 119 LEAD BGA
PIN DESCRIPTIONS
BGA PINS
4P, 4N, 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 5L, 3G
TQFP PINS
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 80, 48, 47, 46, 45, 44, 49, 50 93, 94
SYMBOL A0-A17
TYPE
Input-
Addresses: These inputs are registered and must meet the setup and hold Synchronous times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. InputByte Write Enables: A byte write enable is LOW for a WRITE cycle and HIGH DQ9-DQ16 and DQP2. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE# being LOW.
WEL#, WEH#
Synchronous for a READ cycle. WEL# controls DQ1-DQ8 and DQP1. WEH# controls
4M 4H
87 88
BWE# GW#
InputInput-
Write Enable: This active LOW input gates byte write operations and must Global Write: This active LOW input allows a full 18-bit WRITE to occur times around the rising edge of CLK.
Synchronous meet the setup and hold times around the rising edge of CLK. Synchronous independent of the BWE# and WEn# lines and must meet the setup and hold
4K
89
CLK
Input-
Clock: This signal registers the addresses, data, chip enables, write control setup and hold times around the clock's rising edge.
Synchronous and burst control inputs on its rising edge. All synchronous inputs must meet
4E 6B
98 92
CE# CE2#
InputInputSynchronous
Chip Enable: This active LOW input is used to enable the device and to gate Chip Enable: This active LOW input is used to enable the device.
Synchronous ADSP#.
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MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A15 A14 A13 A12 A11 A16 A17
DESCRIPTION
Galvantech, Inc. reserves the right to change products or specifications without notice.
GALVANTECH, INC.
PIN DESCRIPTIONS (continued)
BGA PINS
2B 4F 4G
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
TQFP PINS
97 86 83
SYMBOL CE2 OE# ADV#
TYPE
inputSynchronous
DESCRIPTION
Chip enable: This active HIGH input is used to enable the device. Output Enable: This active LOW asynchronous input enables the data output drivers. Address Advance: This active LOW input is used to control the internal advance).
Input Input-
Synchronous burst counter. A HIGH on this pin generates wait cycle (no address
4A
84
ADSP#
Input-
Address Status Processor: This active LOW input, along with CE# being is initiated using the new address.
Synchronous LOW, causes a new external address to be registered and a READ cycle
4B
85
ADSC#
Input-
Address Status Controller: This active LOW input causes device to be A READ or WRITE cycle is initiated depending upon write control inputs.
Synchronous de-selected or selected along with new external address to be registered.
3R
31
MODE
InputStatic
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED BURST.
7T
64
ZZ
InputSnooze: This active HIGH input puts the device in low power Asynchro- consumption standby mode. For normal operation, this input has to be nous either LOW or NC (No Connect). Input/ Output Input/ Output Supply Ground Data Inputs/Outputs: Low Byte is DQ1-DQ8. High Byte is DQ9-DQ16. Input data must meet setup and hold times around the rising edge of CLK. Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is parity bit for DQ9-DQ16. Power Supply: +3.3V -5% and +10% Ground: GND.
6D, 7E, 6F, 7G, 6H, 7K, 58, 59, 62, 63, 68, DQ1-DQ16 6L, 6N, 1D, 2E, 2G, 1H, 69, 72, 73, 8, 9, 12, 2K, 1L, 2M, 1N 13, 18, 19, 22, 23 2P, 7P 4C, 2J, 4J, 6J, 4R 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 74, 24 15, 41,65, 91 17, 40, 67, 90 DQP1, DQP2 VCC VSS
4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76
VCCQ VSSQ NC
I/O Supply Output Buffer Supply: +2.5V or 3.3V I/O Ground Output Buffer Ground: GND No Connect: These signals are not internally connected.
1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 5R, 7R, 1T, 4T, 2U, 3U, 4U, 5U, 6U
1-3, 6, 7, 14, 16, 25, 28-30, 38, 39, 42, 43, 51-53, 56, 57, 66, 75, 78, 79, 80, 95, 96
BURST ADDRESS TABLE (MODE = NC/VCC)
First Address (external)
A...A00 A...A01 A...A10 A...A11
Second Address (internal)
A...A01 A...A00 A...A11 A...A10
Third Address (internal)
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal)
A...A11 A...A10 A...A01 A...A00
BURST ADDRESS TABLE (MODE = GND)
First Address (external)
A...A00 A...A01 A...A10 A...A11
Second Address (internal)
A...A01 A...A10 A...A11 A...A00
Third Address (internal)
A...A10 A...A11 A...A00 A...A01
Fourth Address (internal)
A...A11 A...A00 A...A01 A...A10
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Rev. 11/98
GALVANTECH, INC.
TRUTH TABLE
OPERATION ADDRESS USED CE#
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
CE2#
CE2
ADSP# ADSC#
ADV#
WRITE#
OE#
CLK
DQ
Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst
None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current
H L L L L L L L L L X X H H X H X X H H X H
X X H X H L L L L L X X X X X X X X X X X X
X L X L X H H H H H X X X X X X X X X X X X
X L L H H L L H H H H H X X H X H H X X H X
L X X L L X X L L L H H H H H H H H H H H H
X X X X X X X X X X L L L L L L H H H H H H
X X X X X X X L H H H H H H L L H H H H L L
X X X X X L H X L H L H L H X X L H L H X X
L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H
High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D
Note:
1. 2. 3. 4. 5. 6. 7.
X means "don't care." H means logic HIGH. L means logic LOW. WRITE# = L means [BWE# + WEL#*WEH#]*GW# equals LOW. WRITE# = H means [BWE# + WEL#*WEH#]*GW# equals HIGH. WEL# enables write to DQ1-DQ8 and DQP1. WEH# enables write to DQ9-DQ16 and DQP2. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. Suspending burst generates wait cycle. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time for OE# and staying HIGH throughout the input data hold time. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. ADSP# LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
PARTIAL TRUTH TABLE FOR READ/WRITE
FUNCTION READ READ WRITE one byte WRITE all bytes WRITE all bytes GW# H H H H L BWE# H L L L X WEH# X H L L X WEL# X H H L X
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Rev. 11/98
GALVANTECH, INC.
ABSOLUTE MAXIMUM RATINGS*
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V VIN ...........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ..........................-55oC to +150o Junction Temperature .....................................................+150o Power Dissipation ............................................................1.0W Short Circuit Output Current ..........................................50mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0oC Ta
70C; VCC = 3.3V -5% and +10% unless otherwise noted)
CONDITIONS
Data Inputs (DQxx) All Other Inputs
DESCRIPTION
Input High (Logic 1) voltage Input Low (Logic 0) Voltage Input Leakage Current
SYMBOL
VIHD VIH VIl ILI ILI ILO VOH VOL VCC VCCQ
MIN
2.0 2.0 -0.5 -2 -30 -2 2.4
MAX
VCC+0.3 4.6 0.8 2 30 2 0.4
UNITS
V V V uA uA uA V V V V
NOTES
1, 2 1, 2 1, 2 14
0V < VIN < VCC
MODE and ZZ Input Leakage 0V < VIN < VCC Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage I/O Supply Voltage Output(s) disabled, 0V < VOUT < VCC IOH = -5.0mA IOL = 8.0mA
1, 11 1, 11 1 1
3.135 3.135
3.6 VCC
DESCRIPTION
Power Supply Current: Operating CMOS Standby
CONDITIONS
Device selected; all inputs < VILor > VIH;cycle time > tKC MIN; VCC =MAX; outputs open Device deselected; VCC = MAX; all inputs < VSS +0.2 or >VCC -0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH ; all inputs static; VCC = MAX; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; VCC = MAX; CLK cycle time > tKC MIN
SYM
Icc
TYP
150
-3
425
-4
400
-5
375
-6
350
UNITS NOTES
mA 3, 12, 13
ISB2
5
10
10
10
10
mA
12,13
TTL Standby
ISB3
10
20
20
20
20
mA
12,13
Clock Running
ISB4
40
90
80
70
60
mA
12,13
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Rev. 11/98
GALVANTECH, INC.
AC ELECTRICAL CHARACTERISTICS
(Note 5) (0oC
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
TA 70oC; VCC = 3.3V -5% and +10%)
-3 166MHz
SYM MIN MAX
DESCRIPTION
Clock Clock cycle time Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE to output valid OE to output in Low-Z OE to output in High-Z Setup Times Address, Controls and Data In Hold Times Address, Controls and Data In
t t t t t t t t
-4 150MHz
MIN MAX
-5 133MHz
MIN MAX
-6 117MHz
MIN MAX UNITS NOTES
KC KH KL
6.0 2.4 2.4 3.5 1.5 0 1.5 0 3.5 1.5 0.5 6.0 3.5
6.7 2.6 2.6 3.8 1.5 0 1.5 0 3.5 1.5 0.5 6.7 3.5
7.5 2.8 2.8 4.0 1.5 0 1.5 0 3.8 1.5 0.5 7.5 3.8
8.5 3.4 3.4 4.0 1.5 0 1.5 0 3.8 2.0 0.5 8.5 3.8
ns ns ns ns ns ns ns ns ns ns ns ns 4, 6,7 4, 6,7 9 4, 6,7 4, 6,7 10 10
t
t
KQ
KQX
KQLZ OEQ
KQHZ
t
t
OELZ
OEHZ S
H
CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
TA = 25oC; f = 1 MHz VCC = 3.3V
SYMBOL
CI CO
TYP
4 7
MAX
5 8
UNITS
pF pF
NOTES
4 4
THERMAL CONSIDERATION
DESCRIPTION
Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Case
CONDITIONS
Still air, soldered on 4.25 x 1.125 inch 4-layer PCB
SYMBOL
JA JC
TQFP TYP
25 9
UNITS
o o
NOTES
C/W C/W
TYPICAL OUTPUT BUFFER CHARACTERISTICS
OUTPUT HIGH VOLTAGE
VOH (V) -0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 3.4
PULL-UP CURRENT
(m) in (m) ax -38 -38 -38 -26 -20 0 0 0 0 -105 -105 -105 -83 -70 -30 -10 0 0
OUTPUT LOW VOLTAGE
VOL (V) -0.5 0 0.4 0.8 1.25 1.6 2.8 3.2 3.4
PULL-DOWN CURRENT
L(m) in L(m) ax 0 0 10 20 31 40 40 40 40 0 0 20 40 63 80 80 80 80
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GALVANTECH, INC.
AC TEST CONDITIONS Input pulse levels Input slew rate Input timing reference levels Output reference levels Output load
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
OUTPUT LOADS 0V to 3V 1.0V/ns 1.5V 1.5V
DQ Z0 = 50 50 Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT 3.3v 317 DQ 351 5 pF
See Figures 1 and 2
Fig. 2 OUTPUT LOAD EQUIVALENT
NOTES
1. 2. 3. 4. 5. 6. 7. 8. All voltages referenced to VSS (GND). Overshoot: Undershoot: VIH +6.0V for t tKC /2. VIL -2.0V for t tKC /2
15. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1.
Icc is given with no output current. Icc increases with greater output loading and faster cycle times. This parameter is sampled. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. Output loading is specified with CL=5pF as in Fig. 2. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. A READ cycle is defined by byte write enables all HIGH or ADSP# LOW along with chip enables being active for the required setup and hold times. A WRITE cycle is defined by one byte or all byte WRITE per READ/WRITE TRUTH TABLE. OE# is a "don't care" when a byte write enable is sampled LOW.
9.
10. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for "don't care" as defined in the truth table. 11. AC I/O curves are available upon request. 12. "Device Deselected" means the device is in POWER -DOWN mode as defined in the truth table. "Device Selected" means the device is active. 13. Typical values are measured at 3.3V, 25oC and 8.5ns cycle time. 14. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of +30 A.
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GALVANTECH, INC.
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
READ TIMING
tKC t
KL
CLK
t
S
t
KH
ADSP#
t
H
ADSC#
t
S
ADDRESS WEL#, WEH#, BWE#, GW# CE# (See Note)
A1
t
A2
H
t
S
ADV#
t
H
OE#
tKQ tKQLZ tOELZ t
OEQ Q(A2)
tKQ
DQ
Q(A1)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
SINGLE READ
BURST READ
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
November 6, 1998
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Rev. 11/98
GALVANTECH, INC.
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
WRITE TIMING
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS WEL#, WEH#, BWE# GW# CE# (See Note)
A1
tH
A2
A3
tS
ADV#
tH
OE#
tOEHZ tKQX
DQ
Q
D(A1)
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
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Rev. 11/98
GALVANTECH, INC.
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
READ/WRITE TIMING
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS WEL#, WEH#, BWE#, GW# CE# (See Note) ADV#
A1
A2
tH
A3
A4
A5
OE#
DQ
Q(A1) Single Reads
Q(A2)
D(A3) Single Write
Q(A3) Pass Through
Q(A4)
Q(A4+1) Burst Read
Q(A4+2)
D(A5)
D(A5+1)
Burst Write
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
November 6, 1998
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Rev. 11/98
GALVANTECH, INC.
100 Pin TQFP Package Dimensions
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
16.00 + 0.10 14.00 + 0.10
#1
20.00 + 0.10
22.00 + 0.10
1.40 + 0.05
1.60 Max Note: All dimensions in Millimeters
0.65 Basic
0.30 + 0.08
0.60 + 0.15
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Rev. 11/98
GALVANTECH, INC.
7 x 17 (119-lead) BGA Dimensions
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
22.00 + 0.20 20.32 1.27
7 6
14.00 + 0.20
5
7.62
4 3 2 1
1.27
UT R P NML KJ
HGFEDCBA
o 0.75+0.15 (119X)
BOTTOM VIEW
19.50 + 0.10
12.00 + 0.10
0.70 REF.
0.90 + 0.10
30 TYP.
0.56 REF.
0.60 + 0.10
SIDE VIEW
Note: All dimensions in Millimeters
November 6, 1998
13
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 11/98
2.40 MAX.
PIN 1A CORNER
TOP VIEW
GALVANTECH, INC.
Ordering Information
GVT71256D18 256K X 18 SYNCHRONOUS BURST SRAM
GVT 71256D18 X - X
Galvantech Prefix Part Number Speed (3 = 3.5ns access/6.0ns cycle 4 = 3.8ns access/6.7ns cycle 5 = 4.0ns access/7.5ns cycle 6 = 4.0ns access/8.5ns cycle) Package (B = 119 LEAD BGA, T = 100 PIN TQFP)
November 6, 1998
14
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 11/98

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